ECP5 Family

A few of the high-performance features that the ECP5/ECP5-5G line of FPGA devices are designed to provide in a cheap FPGA fabric include a high-performance DSP architecture, high-speed SERDES (Serializer/Deserializer), and high-speed source synchronous interfaces. This combination of advances in device architecture and the use of 40 nm technology makes the devices suitable for high-volume, high-speed, and low-cost applications. The ECP5/ECP5-5G device family has a look-up-table (LUT) capacity of 84K logic components and supports up to 365 users I/O. A high-performance DSP architecture, high-speed SERDES (Serializer/Deserializer), and high-speed source synchronous interfaces are just a few of the high-performance characteristics that the ECP5/ECP5-5G range of FPGA devices are intended to offer in a low-cost FPGA fabric. The utilization of 40 nm technology in conjunction with improvements in device architecture makes the devices appropriate for high-volume, high-speed, and low-cost applications. The ECP5/ECP5-5G device family supports up to 365 user I/O and has a look-up-table (LUT) capacity of 84K logic components. 

The pre-engineered source synchronous logic of the ECP5/ECP5-5G device family supports a broad range of interface protocols, including DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS. Another component of the ECP5/ECP5-5G device family is high-speed SERDES with particular Physical Coding Sublayer (PCS) features. Due to their high jitter tolerance and low transmit jitter, the SERDES plus PCS blocks can be used to support a number of popular data protocols, such as PCI Express, Ethernet (XAUI, GbE, and SGMII), and CPRI. The SERDES's Receive Equalization settings and Transmit De-emphasis with pre- and post-cursors make it suitable for transmission and reception via a range of media. Along with bit-stream encryption, dual boot support, and TransFR field upgrading features, the ECP5/ECP5-5G devices also provide flexible, trustworthy, and secure configuration options. ECP5-5G family devices have improved in the SERDES as compared to ECP5UM devices. The SERDES can now run at up to 5 Gb/s of data rate thanks to these upgrades.

Pin-to-pin compatibility exists between ECP5UM devices and devices from the ECP5-5G series. These allow you to transfer designs for devices with better performance from ECP5UM to ECP5-5G devices.The Lattice Diamond design software enables efficient implementation of large complex designs using the ECP5/ECP5-5G FPGA family. Support for synthesis libraries for ECP5/ECP5-5G devices is available in popular logic synthesis tools. Diamond tools use the output from the synthesis tool and the constraints from its floor planning tools to install and route the design in the ECP5/ECP5-5G device. The tools take the time from the routing and back-annotate it into the design for timing verification.

Lattice provides a range of pre-engineered IP (Intellectual Property) modules for the ECP5/ECP5-5G family. When using these flexible soft core IPs as standardized building blocks, designers have more freedom to concentrate on the unique aspects of their designs, which increases productivity.

Features

 Higher Logic Density for Increased System Integration

 12K to 84K LUTs

 197 to 365 user programmable I/O

 Embedded SERDES

 270 Mb/s, up to 3.2 Gb/s, SERDES interface (ECP5)

 270 Mb/s, up to 5.0 Gb/s, SERDES interface (ECP5-5G)

 Supports eDP in RDR (1.62 Gb/s) and HDR (2.7 Gb/s)

 Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI

 sysDSP

 Fully cascadable slice architecture

 12 to 160 slices for high performance multiply and accumulate

 Powerful 54-bit ALU operations

 Time Division Multiplexing MAC Sharing

 Rounding and truncation

 Each slice supports

 Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers

 Advanced 18 x 36 MAC and 18 x 18 Multiply-Multiply-Accumulate (MMAC) operations

 Flexible Memory Resources

 Up to 3.744 Mb sysMEM Embedded Block RAM (EBR)

 194K to 669K bits distributed RAM

 sysCLOCK Analog PLLs and DLLs

 Four DLLs and four PLLs in LFE5-45 and LFE5-85; two DLLs and two PLLs in LFE5-25 and LFE5-12

 Pre-Engineered Source Synchronous I/O

 DDR registers in I/O cells

 Dedicated read/write levelling functionality

 Dedicated gearing logic

 Source synchronous standards support

 ADC/DAC, 7:1 LVDS, XGMII

 High Speed ADC/DAC devices

 Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate

 Programmable sysI/O Buffer Supports Wide Range of Interfaces

 On-chip termination

 LVTTL and LVCMOS 33/25/18/15/12

 SSTL 18/15 I, II

 HSUL12

 LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

 subLVDS and SLVS, SoftIP MIPI D-PHY receiver/transmitter interfaces

 Flexible Device Configuration

 Shared bank for configuration I/O

 SPI boot flash interface

 Dual-boot images supported

 Slave SPI

 TransFR I/O for simple field updates

 Single Event Upset (SEU) Mitigation Support

 Soft Error Detect – Embedded hard macro

 Soft Error Correction – Without stopping user operation

 Soft Error Injection – Emulate SEU event to debug system error handling

 System Level Support

 IEEE 1149.1 and IEEE 1532 compliant

 Reveal Logic Analyzer

 On-chip oscillator for initialization and general use

 1.1 V core power supply for ECP5, 1.2 V core power supply for ECP5UM5G